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1 of 11 features ? upgrade and drop - in r eplacement for ds2400 extended 2.8 v to 6.0 v rang e multiple ds2401 devices c an r eside on a c ommon 1 - wire ? net ? unique, factory - las ered and t ested 64- bit registration number (8 - bit famil y co de + 48- bit serial number + 8 - bit crc t ester); guaranteed no two parts a like ? built - in multidrop controller ensures compatibility with other 1 - wire net products ? 8- bit family code specifies ds2401 communications requireme nts to r eader ? presence puls e a cknowledges w hen the reader first applies volta ge ? low -c ost to - 92, sot - 223, and tsoc surface - mount packages ? reduces control, a ddress, d ata, and p ower to a single pin ? zero standby power re quired ? directly c onnects to a single port pi n of a m icroprocessor and c ommunicates at u p to 16.3kbps ? to - 92 tape - and - reel ve rsion with leads b ent to 100 - mil sp acing ( d efault) or with straight leads (ds2401- sl) ? - 40c to +85c industrial temperature range applications pcb identification network node id equip ment registration pin configurations 1 2 01rrd flip chip, top view with laser mark, contacts not visible. ?rrd? = revision/date pin description s pin to - 92, sot - 223 tsoc flip chip 1 ground ground data (dq) 2 data (dq) data (dq) ground 3 no connect no connect 4 ground * no connect 5 , 6 no connect * sot - 223 only. ds2401 silicon serial number top view top view bottom view to - 92 ds2401 2 3 1 1 2 3 1 - wire is a registered trademark of maxim integrated products, inc. 19 - 5860 ; rev 5 / 11 tsoc
ds2401 2 of 11 ordering information part temp range pin - package ds24 01+ - 40 c to +85 c 3 to - 92 ds2401+t&r -40 c to +85 c 3 to - 92 (formed leads) ds2401 - sl+t&r - 40 c to +85 c 3 to - 92 (straigh t leads) ds2401 p + - 40 c to +85 c 6 tsoc ds2401 p +t&r - 40 c to +85 c 6 tsoc ds2401 z + -40 c to +85 c 4 sot - 2 23 ds2401 z +t&r - 40 c to +85 c 4 sot - 223 ds2401x1 - s#t - 40 c to +85 c 2 flip chip (2.5k pieces) + denotes a lead(pb) - free/rohs - compliant package. t&r /t = tape and reel. sl = straight leads. # denotes a rohs - compliant device that may include lead that is exempt under the rohs requirements . description the ds2401 enhanced silicon serial number is a low - cost, electronic registration number that provide s an absolutely unique identity which can be determined with a minimal electronic interface (typically, a single port pin of a microcontroller). the ds2401 consists of a factory - lasered, 64 - bit rom that includes a unique 48 - bit serial number, an 8 - bit crc, and an 8 - bit family code (01h). data is transferred serially via the 1 - wire protocol that requires only a single data lead and a ground return. power for reading and writing the device is derived from the data line itself with no need for an external power source. the ds2401 is an upgrade to the ds2400. the ds2401 is fully reverse - compatible with the ds2400 but provides the additional multi - drop capability that enables many devices to reside on a single data line. the familiar to - 92, sot - 223 or tsoc packag e provides a co mpact enclosure that allows standard assembly equipment to handle the device easily. operation the ds2401s internal rom is accessed via a single data line. the 48 - bit serial number, 8 - bit family code and 8 - bit crc are retrieved using the maxim 1- wire protocol. this protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. all data is read and written least significant bit first. 1- wire bus system the 1 - wire bus is a system which has a single bus master system and one or more slaves. in all instances, the ds2401 is a slave device. the bus master is typically a microcontroller. the discussion of this bus system is broken down into t hree topics: hardware configuration, transaction sequence, and 1 - wire signaling (signal type and timing). hardware configuration the 1 - wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1 - wire bus must have an open - drain connection or 3 - state outputs. the ds2401 is an open - drain part with an internal circuit equivalent to that shown in figure 2. the bus master can be the sam e equivalent circuit. if a bidirectional pin is not available, separate output and input pins can be tied together. the bus master requires a pullup resistor at the master end of the bus, with the bus master circuit equivalent to the one shown in figure 3. the value of the pullup resistor should be approximately 5k ? for short line lengths. a multidrop bus consists of a 1 - wire bus with multiple slaves attached. the 1 - wire bus has a maximum data rate of 16.3kbits per second.
ds2401 3 of 11 the idle state for the 1 - wire bus is high. if, for any reason, a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 120 s, one or more of the devices on the bus may be res et. ds2401 memory map figure 1 8- bit crc code 48- bit serial number 8- bit family code (01h) msb lsb msb lsb msb lsb ds2401 equivalent circuit figure 2 bus master circuit figure 3 a) open drain note: depending on the 1 - wire communication speed and the bus load characteristics, the optimal pullup resistor (r pu ) value will be in the 1.5k ? to 5k ? range. to data connection of ds2401 b) standard ttl to data connection of ds2401 see note see note v pup v pup
ds2401 4 of 11 transactio n sequence the sequence for accessing the ds2401 via the 1 - wire port is as follows: ? initialization ? rom function command ? read data initialization all transactions on the 1 - wire bus begin with an initialization sequence. the initialization sequence consi sts of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds2401 is on the bus and is ready to operate. for more details, see the 1 - wire signaling section. rom function commands once the bus master has detected a presence, it can issue one of the four rom function commands. all rom function commands are 8 bits long. a list of these commands follows (refer to flowchart in figure 4). read rom [33h] o r [0fh] this command allows the bus master to read the ds2401s 8 - bit family code, unique 48 - bit serial number, and 8 - bit crc. this command can only be used if there is a single ds2401 on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired - and result). the ds2401 read rom function will occur with a command byte of either 33h or 0fh in order to ensure compatibility with the ds2400, which will only respond to a 0fh command word with its 64 - bit rom data. match rom [55h] / skip rom [cch] the complete 1 - wire protocol for all maxim i buttons ? contains a match rom and a skip rom command. since the ds2401 contains only the 64 - bit rom w ith no additional data fields, the match rom and skip rom are not applicable and will cause no further activity on the 1 - wire bus if executed. the ds2401 does not interfere with other 1 - wire parts on a multidrop bus that do respond to a match rom or skip rom (for example, a ds2401 and ds1994 on the same bus). search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1 - wire bus or their 64 - bit rom codes. the search rom command allows the bus master to use a process of elimination to identify the 64 - bit rom codes of all slave devices on the bus. the rom search process is the repetition of a simple 3 - step routine: read a b it, read the complement of the bit, then write the desired value of that bit. the b us master performs this simple 3 - step routine on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. the remaining number of devices and their rom codes may be identified by additional passes. refer to application note 187: 1 - wire search algorithm for a comprehensive discussion of a rom search, including an actual example. i button is a registered trademark of maxim integrated products, inc.
ds2401 5 of 11 1- wire signaling the ds2401 requires a strict protocol to ensure data integrity. the protocol consists of four types of signal ing on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, and read data. all these signals except presence pulse are initiated by the bus master. the initialization sequence required to begin any communication with the ds2401 is shown in figure 5. a reset pulse followed by a presence pulse indicates the ds2401 is ready to send or receive data given the correct rom command. the bus master transmits (t x ) a r eset pulse (t rstl , minimum 480 s). the bus master then releases the l ine and goes into receive mode (r x ). the 1 - wire bus is pulled to a high state via the 5k ? pullup resistor. after detecting the rising edge on the data pin, the ds2401 waits (t pdh , 15 -60 s) and then transmits the presence pulse (t pdl , 60 -240 s). the 1 - wire bus requires a pullup resistor range of 1.5k ? to 5k ? , depending on bus load characteristics. read/write time slots the definitions of write and read time slots are illustrated in figure 6. all time slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the ds2401 to the master by triggering a delay circuit in the ds2401. during write time slots, the delay circuit determines when the ds2401 will sample the data line. for a read data time slot, if a 0 is to be transmitted, the delay circuit determines how long the ds2401 will hold the data line low overriding the 1 generated by the master. if the data bit is a 1, the ds2401 will leave the read data time slot unchanged.
ds2401 6 of 11 rom functions flow chart figure 4
ds2401 7 of 11 initialization procedure ?reset and presence pulses? figure 5 480 s t rstl < * 480 s t rsth < (includes recovery time) 15 s t pdh < 60 s 60 s t pdl < 240 s ? in order not to mask interrupt signaling by other devices on the 1 - wire bus, t rstl + t r should always be less than 960 s. read/write timing diagram figure 6 write - one time slot 60 s t slot < 120 s 1 s t low1 < 15 s 1 s t rec < resistor master resistor master ds2401
ds2401 8 of 11 read/write timing diagram (cont?d) figure 6 write - zero time slot 60 s t low0 < t slot < 120 s 1 s t rec < read - data time slot 60 s t s lot < 120 s 1 s t lowr < 15 s 0 t release < 45 s 1 s t rec < t rdv = 15 s t su < 1 s crc generation to validate the data transmitted from the ds2401, the bus master may generate a c rc value from the data as it is received. this generated value is compared to the value stored in the last 8 bi ts of the ds2401. if the two crc values match, the transmission is error - free. the equivalent polynomial function of this crc is: crc = x 8 + x 5 + x 4 + 1. additional information about the maxim 1- wir e crc is available in application note 27 . custom ds2401 customization of a portion of the unique 48 - bit serial number by the customer is available. maxim will register and assign a specific customer id in the 12 most significant bits of the 48 - bit field. the next most significant bits are selectable by the customer as a starting value, and the least significant bits are non - selectable and will be automatically incremented by one. certain quantities and conditions apply for these custo m parts. contact your maxim sales representative for more information. resistor master ds2401
ds2401 9 of 11 absolute maximum ratings voltage range on a ny pin relative to ground - 0.5v to +7.0v operating temperature range -40 c to +85 c storage temperature ran ge -55 c to +125 c lead temperature (to - 92, tsoc, sot - 223 only; soldering, 10s) +300 c soldering temperature (reflow) to -92 +250 c tsoc, sot -223 +260 c flip chip +240 c this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (t a = -40 c to +85 c, unless otherwise noted. ) parameter symbol min typ max units notes pullup voltage v pup 2.8 6.0 v 2 logic 1 v ih 2.2 v 1, 6 logic 0 v il - 0.3 +0.3 v 1 output logic - low at 4 ma v ol 0.4 v 1 input load current i l 5 a 3 operating charge q op 30 nc 7, 8 capacitance (t a = +25 c , u nless otherwise noted. ) parameter symbol min typ max units notes i/o (1 - wire) c in/out 800 pf 9 ac electrical characteristics (t a = - 40c to +85c , unless otherwise noted. ) parameter symbol min typ max units notes time slot t slot 60 120 s write 1 low time t low1 1 15 s 12 write 0 low time t low0 60 120 s read data valid t rdv 15 s 11 release time t release 0 15 45 s read data setup t su 1 s 5 recovery time t rec 1 s reset time high t rsth 480 s 4 rese t time low t rstl 480 960 s 10 presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s
ds2401 10 of 11 notes: 1) all voltages are referenced to ground. 2) v pup = external pullup voltage. 3) input load is to ground. 4) an additional reset or communication sequence cannot begin until the reset high time has expired. 5) read data setup time refers to the time the host must pull the 1 - wire bus low to read a bit. data is guaranteed to be valid within 1 s of this falling edge and will remain valid for 14 s minimum (15 s total from falling edge on 1 - wire bus). 6) v ih is a function of the external pullup resistor and v pup . 7) 30 nanocoulombs per 72 time slots at 5.0v. 8) at v pup = 5.0v with a 5k ? pullup to v pup and a maximum time slot of 120 s. 9) capa citance on the i/o pin could be 800pf when power is first applied. if a 5k ? resistor is used to pullup the i/o line to v pup , 5 s after power has been applied the parasite capacitance will not affect normal communications. 10) the reset low time (t rstl ) sho uld be restricted to a maximum of 960 s, to allow interrupt signaling, otherwise it could mask or conceal interrupt pulses if this device is used in parallel with a ds2404 or ds1994. 11) the optimal sampling point for the master is as close as possible to th e end time of the t rdv period without exceeding t rdv . for the case of a read - one time slot, this maximizes the amount of time for the pullup resistor to recover to a high level. for a r ead - zero time slot, it ensures that a r ead will occur before the fastes t 1 - wire device(s) releases the line. 12) the duration of the low pulse sent by the m aster should be a minimum of 1s with a maximum value as short as possible to allow time for the pullup resistor to recover the line to a high level before the 1- wire device samples in the case of a write - one time or before the master samples in the case of a read - one time. package information for the latest package outline information and land patterns (footprints) , go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicat es rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 3 to - 92 (straight leads) q3+1 21-0248 3 to - 92 (formed leads) q3+4 21-0250 6 tsoc d6+1 21-0382 90-0321 4 sot -223 k3+1 21-0264 2 flip chip bf211#1 21-0378 refer to 21-0378
ds2401 11 of 11 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 20 11 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision date description pages changed 040601 changed microlan to 1 - wire net; updated ordering information for tape an d reel 1 changed soldering temperature from 260c for 10 seconds to see j - std - 020a specification 9 022202 below f igure 3, added a note on the optimal r pup range ; a dded a similar note before the read/write time slots section 3, 6 added notes 11 to 1 3 to the ec table 9, 10 122106 added flip chip package; added l ead - free ordering information 1, 2 references to the book of i button standards replaced with references to corresponding application notes various v il max changed from 0.8v to 0.3v, ec tabl e note 11 deleted 9, 10 5/11 deleted standard (pb) parts from ordering information ; c hanged flip chip part number from ds2401x1 to ds2401x1 -s#t 2 deleted v oh from the ec table ; m oved v pup from the ec table header into the ec table ; c hanged sol dering temperature from j - std -020a reference to explicit package specific numbers 9 added package information and revision history section s 10, 11

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